Passive Chip Device and Method of Making the Same

ABSTRACT

A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of Taiwanese Application No. 104120533,filed on Jun. 25, 2015.

FIELD

The disclosure relates to a passive chip device and a method of makingthe same, more particularly to a passive chip device with terminalcontacts.

BACKGROUND

A passive device is referred to as a circuit device that is not capableof providing power gain. A capacitor, an inductor, and a resistor areall considered as passive devices. There are three types of commerciallyavailable inductors namely thin film type inductors, multilayered typeinductors, and wire wound type inductors.

TW patent application publication No. 201440090 A discloses amultilayered type inductor (see FIG. 1) and a method of making the same.

The method of making the multilayered type inductor includes the stepsof: laminating a first circuit plate 110, a second circuit plate 120, athird circuit plate 130 and a fourth circuit plate 140 (see FIG. 2A);attaching an assembly of a supporting film 150 and a bonding pad circuit160 to the first circuit plate 110 (see FIG. 2B); transferring thebonding pad circuit 160 from the supporting film 150 to the firstcircuit plate 110 (see FIG. 2C); removing the supporting film 150 fromthe bonding pad circuit 160 (see FIG. 2D); sintering the first, second,third and fourth circuit plates 110, 120, 130, 140 and the bonding padcircuit 160 so as to form a multilayered substrate 100 (see FIG. 2E);and scribing the multilayered substrate 100 using a scriber 170 (seeFIG. 2F), so that the multilayered substrate 100 can be broken into aplurality of multilayered type inductors 10 (see FIG. 1).

Referring to FIG. 1, each of the first, second, third and fourth circuitplates 110, 120, 130, 140 includes a respective one of non-magneticbodies 111, 121, 131, 141 and a respective one of first, second, thirdand fourth circuit patterns 112, 122, 132, 142. Formation of the first,second, third and fourth circuit plates 110, 120, 130, 140 requiresnumerous steps (a total of at least 13 steps), including punching eachnon-magnetic body 111, 121, 131, 141 to form holes therein, fillingconductive paste in the holes, forming the first, second, third andfourth circuit patterns 112, 122, 132, 142 and sintering beforelaminating the first, second, third and fourth circuit plates 110, 120,130, 140.

The multilayered type inductor 10 thus formed has drawbacks, such asundesired non-ohmic contact and Joule-heating which may be induced atthe interfaces between every two adjacent ones of the first, second,third and fourth circuit patterns 112, 122, 132, 142.

A conventional method of making a thin film type inductor includes stepsof: forming a coil layer (a total of 10 steps); forming an intermediatelayer on the coil layer; forming a top electrode on the intermediatelayer (a total of 6 steps); forming a bottom electrode (a total of 6steps); forming a protecting layer so as to forma layered structure withan array of thin film inductors; forming a plurality of stick-breakinglines and chip-breaking lines in the layered structure; breaking thelayered structure along the stick-breaking lines so as to form inductorsticks; forming side face contacts on each of the inductor sticks;breaking each inductor stick along the chip-breaking lines so as to formthe semi-formed inductor chips; and forming end face contacts on each ofthe semi-formed inductor chips. The end face contacts cooperate with theside face contacts to define terminal contacts of each thin film typeinductor.

The aforesaid method of making the thin film type inductor is relativelycomplicated, such as requiring numerous steps to form the terminalcontacts of each inductor chip.

SUMMARY

Therefore, an object of the disclosure is to provide a passive chipdevice that can alleviate at least one of the drawbacks of the priorarts.

According to one aspect of the disclosure, there is provided a passivechip device that includes a chip body, a conductive coil and asurface-mount contact unit.

The chip body is in the form of a single piece, which extends in anaxial direction, and which has two opposite end faces and a firstsurface. The end faces are opposite to each other in the axialdirection. The first surface extends along the axial direction betweenthe end faces.

The conductive coil is deposited on and surrounds the chip body forgenerating inductance. The conductive coil has two opposite endportions.

The surface-mount contact unit includes two spaced apart conductiveterminal contacts. Each of the terminal contacts extends from arespective one of the end faces to the first surface, and contacts arespective one of the end portions of the coil.

According to another aspect of the disclosure, there is provided apassive chip device that includes a chip body, a capacitor and asurface-mount contact unit.

The chip body is in the form of a single piece, extends in an axialdirection, and has two opposite end faces and first and second surfaces. The end faces are opposite to each other in the axial direction. Thefirst and second surfaces are opposite to each other and extend alongthe axial direction between the end faces.

The capacitor is formed on the chip body, and has first and secondconductive layers and a dielectric layer that is sandwiched between thefirst and second conductive layers and that is disposed adjacent to thesecond surface and distal from the first surface.

The surface-mount contact unit is formed on the chip body and includestwo spaced apart conductive terminal contacts. Each of the terminalcontacts has a first segment overlapping a respective one of the endfaces along the axial direction and contacting a respective one of thefirst and second conductive layers, and a second segment extending fromthe first segment and formed on the first surface.

According to yet another aspect of the disclosure, there is provided amethod of making a surface-mountable passive chip device.

The method includes: forming a patterned wafer which has a peripheralend portion and at least one passive-component unit that includes aconnecting portion, a breaking line, and a plurality of spaced apartchip bodies, the connecting portion being connected to the peripheralend portion, the breaking line having a plurality of connecting tabsthat are spaced apart from one another, each of the connecting tabsbeing disposed between and interconnecting the connecting portion and arespective one of the chip bodies, each of the chip bodies extending inan axial direction and having two opposite end faces and a firstsurface, the end faces being opposite to each other in the axialdirection, the first surface extending along the axial direction betweenthe end faces; forming a functional layered structure on each of thechip bodies; forming a conductive seed layer on the functional layeredstructure on each of the chip bodies; forming a contact-definingpatterned photoresist layer on the conductive seed layer on each of thechip bodies, such that two opposite end portions of the conductive seedlayer, which are respectively disposed adjacent to the end faces of eachof the chip bodies, are exposed from the contact-defining patternedphotoresist layer; forming a surface-mount contact unit having twospaced apart conductive terminal contacts that are respectively formedon the end portions of the conductive seed layer on each of the chipbodies, each of the conductive terminal contacts being electro-connectedto the functional layered structure and extending from a respective oneof the end faces to the first surface; removing the contact-definingpatterned photoresist layer and the remaining portion of the conductiveseed layer that is covered by the contact-defining patterned photoresistlayer; and breaking the patterned wafer along the breaking line byapplying an external force thereto so as to form a plurality of passivechip devices.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the disclosure will become apparent inthe following detailed description of the embodiments with reference tothe accompanying drawings, of which:

FIG. 1 is an exploded perspective view of a multilayered type inductordisclosed in TW patent application publication No. 201440090 A;

FIGS. 2A to 2F are sectional views illustrating consecutive steps of amethod of making the multilayered type inductor of FIG. 1;

FIG. 3 is a perspective view illustrating the first embodiment of apassive chip device according to the disclosure;

FIG. 4 is a perspective view illustrating the second embodiment of thepassive chip device according to the disclosure;

FIG. 5 is a side view illustrating the third embodiment of a passivechip device according to the disclosure;

FIG. 6 is a top view illustrating a patterned wafer formed in step S1 ofa method of making the first embodiment of the passive chip deviceaccording to the disclosure;

FIG. 7 is an enlarge view of an encircled portion of FIG. 6;

FIG. 8 is a perspective view illustrating a passive-component unit ofthe patterned wafer shown in FIG. 6

FIG. 9 is a fragmentary top view illustrating a patterned photoresistlayer used in step S1 of the method of making the first embodiment ofthe passive chip device according to the disclosure;

FIG. 10 is a sectional view taken along line X-X of FIG. 10;

FIG. 11 is a fragmentary top view illustrating an etching procedure usedin step S1 of the method of making the first embodiment of the passivechip device according to the disclosure;

FIG. 12 is a sectional view taken along line XII-XII of FIG. 12;

FIGS. 13A to 13H are perspective views illustrating steps S2 to S6 ofthe method of making the first embodiment of the passive chip deviceaccording to the disclosure;

FIG. 14 is a fragmentary top view illustrating step S7 of the method ofmaking the first embodiment of the passive chip device according to thedisclosure;

FIG. 15 is a fragmentary side view illustrating the first embodiment ofa passive chip device according to the disclosure mounted to a circuitplate;

FIGS. 16A to 16C are perspective views illustrating consecutive steps ofthe method of making the second embodiment of the passive chip deviceaccording to the disclosure; and

FIGS. 17A to 17C are perspective views illustrating consecutive steps ofthe method of making the third embodiment of the passive chip deviceaccording to the disclosure.

DETAILED DESCRIPTION

Before the disclosure is described in greater detail, it should be notedthat like elements are denoted by the same reference numerals throughoutthe disclosure.

Referring to FIG. 3, the first embodiment of the passive chip deviceincludes a chip body 2, a conductive coil 3, and a surface-mount contactunit 4.

The chip body 2 is in the form of a single piece, and thus has a highermechanical strength than that of the conventional multilayered inductor.The chip body 2 extends in an axial direction (X), and has two oppositeend faces 21 and a first surface 22. The end faces 21 are opposite toeach other in the axial direction (X). The first surface 22 extendsalong the axial direction (X) between the end faces 21.

The conductive coil 3 is deposited on and surrounds the chip body 2 forgenerating inductance. The conductive coil 3 has two opposite endportions 31. The surface-mount contact unit 4 includes two spaced apartconductive terminal contacts 41. Each of the terminal contacts 41extends from a respective one of the end faces 21 to the first surface22, and contacts a respective one of the end portions 31 of theconductive coil 3.

The conductive terminal contacts 41 of the surface-mount contact unit 4are made from a material containing Ni and a metal selected from thegroup consisting of Au and Sn.

The chip body 2 may be made from a magnetic material or a non-magneticmaterial. The magnetic material is magnetic metal or magnetic ceramic.The non-magnetic material is a Si-based material or non-magnetic metal.The magnetic metal may be Fe, Co or Ni. The magnetic ceramic may be aferrite (Fe₃O₄) with an inverse spinel structure. In certainembodiments, the chip body 2 is made from magnetic metal, so that thepassive chip device is a magnetic-core inductor. The Si-based materialmay be quartz, a Si wafer, Si₃N₄, or SiC. The non-magnetic metal may beCu. In certain embodiments, the chip body 2 is made from quartz, so thatthe passive chip device is an air-core inductor.

When the chip body 2 is made from the magnetic metal or the non-magneticmetal, the first embodiment of the passive chip device further includesan insulator layer (not shown) which is formed on the chip body 2. Theconductive coil 3 is deposited on the insulator layer, so as to preventthe passive chip device from short circuit.

Referring to FIG. 4, the second embodiment differs from the firstembodiment in that the chip body 2 further has a second surface 23 whichis opposite to the first surface 22 and which extends along the axialdirection (X) between the end surfaces 21. Each of the terminal contacts41 further extends from the respective one of the end faces 21 to thesecond surface 23.

Referring to FIG. 5, the third embodiment differs from the firstembodiment in that the third embodiment includes a capacitor 5 insteadof the conductive coil 3.

The capacitor 5 is formed on the chip body 2 and has first and secondconductive layers 51, 52 and a dielectric layer 53 that is sandwichedbetween the first and second conductive layers 51, 52 and that isdisposed adjacent to the second surface 23 and distal from the firstsurface 22.

Each of the terminal contacts 41 has a first segment 411 overlapping arespective one of the end faces 21 and contacting a respective one ofthe first and second conductive layers 51, 52, and a second segment 412extending from the first segment 411 and formed on the first surface 22.

In this embodiment, the first conductive layer 51 is formed on thesecond surface 23 and a respective one of the end faces 21. The secondconductive layer 52 is formed on the first conductive layer 51 and theother respective one of the end faces 21. The first segment 411 isformed on and electrically connected to the respective one of the firstand second conductive layers 51, 52.

The following description illustrates a method of making the passivechip device of the first embodiment of the disclosure, and should not beconstrued as limiting the scope of the disclosure. The method includesthe steps of S1 to S7.

In step S1 (see FIGS. 6 to 8), a patterned wafer 61 which has aperipheral end portion 610 and at least one passive-component unit 611that includes a connecting portion 6111, a breaking line 6112, and aplurality of spaces apart chip bodies 2, is formed. The connectingportion 6111 is connected to the peripheral end portion 610. Thebreaking line 6112 has a plurality of connecting tabs 6114 that arespaced apart from one another. Each of the connecting tabs 6114 isdisposed between and interconnecting the connecting portion 6111 and arespective one of the chip bodies 2. Each of the chip bodies 2 has astructure as mentioned above.

The patterned wafer 61 is formed from a wafer 60 using etchingtechniques or punching techniques.

In certain embodiments (see FIGS. 9 to 12), the wafer 60 may be madefrom quartz, and two first patterned photoresist layers 71 arerespectively formed on top and bottom surfaces 603, 604 of the wafer 60,such that each of the top and bottom surfaces 603, 604 of the wafer 60has wider exposed regions 601 and narrow exposed regions 602 which areexposed from the respective one of the first patterned photoresistlayers 71. The narrow exposed regions 602 have an etching rate less thanthose of the wider exposed regions 601. The wafer 60 is subsequentlypatterned using etching techniques so as to form the patterned wafer 61.

Each of the connecting tabs 6114 is reduced in width (D) from theconnecting portion 6111 toward the respective one of the chip bodies 2.Each of the connecting tabs 6114 has a thickness (T) less than that ofthe connecting portions 6111 and that of the chip bodies 2.

In certain embodiments, the wafer 60 may be made from the non-magneticmetal or the magnetic metal, and the patterned wafer 61 is formed bypunching techniques using a punching mold (not shown) with an array ofholes. Each of the connecting tabs 6114 is etched or scribed (or cutusing laser cutting techniques) so as to have the thickness (T) lessthan that of the connecting portions 6111 and that of the chip bodies 2.

In certain embodiments, the wafer may be made from ceramic green. Theceramic green is patterned using punching techniques, followed bysintering so as to form the patterned wafer 61 with an improvedmechanism strength.

In step S2 (see FIGS. 13A to 13D), a functional layered structure 9 isformed on each of the chip bodies 2.

In step S2, the forming of the functional layered structure 9 includes:forming a layered structure-defining seed layer 81 on each of the chipbodies 2; forming a layered structure-defining patterned photoresistlayer 82 on the layered structure-defining seed layer 81, such that aregion 810 of the layered structure-defining seed layer 81 is exposedfrom the layered structure-defining patterned photoresist layer 82; andplating a metal layer (not shown) on the exposed region 810 of thelayered structure-defining seed layer 81 so as to form the functionallayered structure 9. In this embodiment, the functional layeredstructure 9 is in the form of the coil 3 which surrounds the respectiveone of the chip bodies 2.

In certain embodiments, when the patterned wafer 61 is made from themagnetic metal or the non-magnetic metal, the step S2 further includes astep of: forming an insulator layer (not shown) on each of the chipbodies 2 before formation of the layered structure-defining seed layer81.

It should be noted that the layered structure-defining seed layer 81 maybe made from a catalytically active material selected from the groupconsisting of Pt, Pd, Au, Ag, and Cu, or a conductive material. When thelayered structure-defining seed layer 81 is made from the catalyticallyactive material, the metal layer is formed through chemical platingtechniques. When the layered structure-defining seed layer 81 is madefrom the conductive material, the metal layer is formed throughelectro-plating techniques.

In this embodiment, the forming of the functional layered structure 9further includes: removing the layered structure-defining patternedphotoresist layer 82 and a portion of the layered structure-definingseed layer 81 that is covered with the layered structure-definingpatterned photoresist layer 82 from each of the chip bodies 2.

In step S3 (see FIG. 13E), a conductive seed layer 84 is formed on thefunctional layered structure 9 on each of the chip bodies 2.

In step S4 (see FIG. 13F), a contact-defining patterned photoresistlayer 83 is formed on the conductive seed layer 84, such that twoopposite end portions 841 of the conductive seed layer 84, which arerespectively disposed adjacent to the end faces 21 of each of the chipbodies 2, are exposed from the contact-defining patterned photoresistlayer 83.

In step S5 (see FIG. 13D to 13G), the surface-mount contact unit 4 of ametal is formed on each of the chip bodies 2. The surface-mount contactunit 4 has two spaces apart conductive terminal contacts 41 that arerespectively formed on the end portions 841 of the conductive seed layer84. Each of the conductive terminal contacts 41 is electro-connected tothe functional layered structure 9 and extends from a respective one ofthe end faces 21 to the first surface 22 of the chip body 2.

In this embodiment, the first surface 22 defines a bottom side of thechip body 2.

It should be noted that the conductive seed layer is made from acatalytically active material selected from the group consisting of Pt,Pd, Au, Ag, and Cu, or a conductive material. When the conductive seedlayer 84 is made from the catalytically active material, thesurface-mount contact unit 4 is formed through chemical platingtechniques. When the conductive seed layer 84 is made from theconductive material, the surface-mount contact unit 4 is formed throughelectro-plating techniques.

In this embodiment, the conductive seed layer 84 is made from thecatalytically active material, and the surface-mount contact unit 4 isformed through chemical plating techniques.

In step S6 (see FIGS. 13F to 13H), the contact-defining patternedphotoresist layer 83 and a remaining portion of the conductive seedlayer 84 that is covered by the contact-defining patterned photoresistlayer 83 are removed.

In step S7 (see FIG. 14), the patterned wafer 61 is broken along thebreaking line 6112 by applying an external force thereto so as to form aplurality of passive chip devices 20.

Referring to FIG. 15, the passive chip device 20 may be mounted to twocontacting points 851 of a circuit plate 85 through the terminalcontacts 41 using a solder 86 by surface-mount techniques.

Referring to FIGS. 4 and 16A to 16C, the method of making the passivechip device of the second embodiment differs from the method of makingthe first embodiment in that each of the terminal contacts 41 furtherextends from a respective one of the end faces 21 to the second surface23 of the chip body 2.

Referring to FIGS. 5 and 17A to 17C, the method of making the passivechip device of the third embodiment differs from the method of makingthe first embodiment in that the functional layered structure 9 is inthe form of the capacitor 5 and is formed by forming a first conductivelayer 51 on the second surface 23 of the chip body 2 and a respectiveone of the end faces 21, forming a dielectric layer 53 on the firstconductive layer 51, and forming a second conductive layer 52 on thedielectric layer 53 and the other respective one of the end faces 21 sothat the dielectric layer 53 is sandwiched between and electricallyisolates the first and second conductive layers 51, 52.

To sum up, the method of the present disclosure may be advantageous overthe prior art in reducing the steps of making the passive chip device.

In addition, the chip body 2 of the passive chip device of the presentdisclosure is in the form of a single piece. As such, the chip body 2 ofthe passive chip device of the present disclosure has a highermechanical strength than that of the conventional multilayered typeinductor.

Furthermore, formation of the first and second segments 411, 412 of theterminal contacts 41 is performed in one single step. Hence, the methodof the present disclosure may alleviate the aforesaid drawback regardingthe requirement of numerous steps in making the terminal contacts in theconventional method of making the thin film type inductors.

While the disclosure has been described in connection with what areconsidered the exemplary embodiments, it is understood that thisdisclosure is not limited to the disclosed embodiments but is intendedto cover various arrangements included within the spirit and scope ofthe broadest interpretation so as to encompass all such modificationsand equivalent arrangements.

What is claimed is:
 1. A passive chip device comprising: a chip bodywhich is in the form of a single piece, which extends in an axialdirection, and which has two opposite end faces and a first surface,said end faces being opposite to each other in said axial direction,said first surface extending along said axial direction between said endfaces; a conductive coil deposited on and surrounding said chip body forgenerating inductance, said conductive coil having two opposite endportions; and a surface-mount contact unit including two spaced apartconductive terminal contacts, each of which extends from a respectiveone of said end faces to said first surface, and each of which contactsa respective one of said end portions of said coil.
 2. The passive chipdevice of claim 1, wherein said conductive terminal contacts of saidsurface-mount contact unit are made from a material containing Ni and ametal selected from the group consisting of Au and Sn, said chip bodybeing made from a magnetic material or a non-magnetic material, saidmagnetic material being magnetic metal or magnetic ceramic, saidnon-magnetic material being a Si-based material or non-magnetic metal.3. The passive chip device of claim 2, further comprising an insulatorlayer formed on said chip body, said chip body being made from saidmagnetic metal or said non-magnetic metal, said conductive coil beingdeposited on said insulator layer.
 4. The passive chip device of claim1, wherein said chip body further has a second surface which is oppositeto said first surface and which extends along said axial directionbetween said end faces, each of said terminal contacts further extendingfrom the respective one of said end faces to said second surface.
 5. Apassive chip device comprising: a chip body which is in the form of asingle piece, which extends in an axial direction, and which has twoopposite end faces and first and second surfaces, said end faces beingopposite to each other in said axial direction, said first and secondsurfaces being opposite to each other and extending along said axialdirection between said end faces; a capacitor which is formed on saidchip body and which has first and second conductive layers and adielectric layer that is sandwiched between said first and secondconductive layers and that is disposed adjacent to said second surfaceand distal from said first surface; and a surface-mount contact unitformed on said chip body and including two spaced apart conductiveterminal contacts, each of which has a first segment overlapping arespective one of said end faces along said axial direction andcontacting a respective one of said first and second conductive layers,and a second segment extending from said first segment and formed onsaid first surface.
 6. The passive chip device of claim 5, wherein saidconductive terminal contacts of said surface-mount contact are made froma material containing Ni and a metal selected from the group consistingof Au and Sn, said chip bodies being made from a magnetic material or anon-magnetic material, said magnetic material being magnetic metal ormagnetic ceramic, said non-magnetic material being a Si-based materialor non-magnetic metal.
 7. The passive chip device of claim 6, furthercomprising an insulator layer formed on said chip body, said chip bodybeing made from said magnetic metal or said non-magnetic metal, saidcapacitor being formed on said insulator layer.